The present invention relates to a method for fabricating integrated circuits. The invention further relates to apparatus for performing the method, and to integrated circuit products of the fabrication method.
It is widely believed that the future of integrated circuits (IC) lies in three-dimensional structures. It is hoped that multiple layer IC circuits will have all the advantages of SOI devices and many other advantages. Specifically, their cell area will be reduced and their circuit density improved. Also, total interconnect lengths are shortened by using vertical connections, thus lowering the RC delay and power consumption.
Such known devices employ a vertical xe2x80x9cmulti-floorxe2x80x9d structure in which multiple layers are separated from their neighbouring layers by insulating films. One of the challenges in developing 3-D technology is to build high quality single crystallised silicon on an insulating material to form the second layer and beyond. Several methods have been reported, such as laser recrystallisation [1], and selective lateral overgrowth epitaxy [2]. However, the methods mentioned are complicated and may cause dislocation defects. Another recent method uses a germanium seed to recrystallize the polysilicon film laterally, but the grain size is limited to few microns [3].
A new recrystallization technique called Metal Induced Lateral Crystallization (MILC) has been proposed [4] to form a high quality silicon film in which thin film transistors (TFT) can be formed. Initially, a 3000 Angstroms layer of oxide is formed on a silicon wafer. 1000 Angstroms of amorphous silicon was deposited at 550xc2x0 C., followed by 3000 Angstroms of low temperature oxide (LTO). An elongate trench was then opened next to the desired region for crystallisation, and 100 Angstroms of Ni was deposited in a layer covering the surface of the structure and in particular covering the bottom and side walls of the trench. Lateral crystallisation was carried out at 550xc2x0 C. for 25 hours. It was found that crystallisation of the amorphous silicon proceeded to either side of the trench such that the interface between the crystallised and amorphous silicon gradually moved away from the trench (analogous to a spreading wavefront) at about 2.5 micrometers per hour. The Ni and LTO were then completely removed, and the wafers subsequently annealed at 900xc2x0 C. for 30 minutes to enlarge the silicon grains. Conventional techniques were then used to form NMOS and PMOS transistors in the grains, and it was found that the grains were large enough that most devices having a 1 micrometer channel length and a channel direction perpendicular to the length direction of the trench, were substantially in a single grain and thus exhibited useful properties. However, devices with a longer channel (e.g. 9 micrometers) could not be formed entirely within a single grain, Furthermore, devices in which the channel length was parallel to the trench length could not be formed entirely within a single grain, even if the channel length was as short as 1 micrometer, since in this direction grain boundaries occurred at random positions. The authors mentioned a couple of applications for the proposed TFTs, including forming 3-D stacked circuits.
The present invention aims to provide new and useful methods and apparatus for integrated circuit fabrication.
In general terms, the present invention proposes that metal-induced lateral crystallisation is performed while controlling the positions of the grain boundaries normal to the crystallisation direction. By doing this, it can be ensured that the grains are correctly positioned for subsequent formation of electronic devices within them.
In a first technique, the grains are positioned by depositing the metal which induces the crystallisation in strips which are only as long as corresponding achievable grains. In other words, each grain is formed due to a corresponding strip, and in a position corresponding to the location of the strip.
In a second technique, which may be used in combination with the first technique, the grains are positioned by a patterning of the amorphous semiconductor which is to be used to form the grains.
Although the invention can be expressed in terms of methods for forming integrated circuits, it also covers apparatus adapted to perform the methods, and to the products of the methods.
The present invention makes it possible to fabricate electronic circuit elements, especially transistors, in a simple and flexible manner.
It further makes it possible to fabricate 3 dimensional structures which, unlike existing 3D structures, may have any number of layers of circuit elements, not just two.
Also, the present invention may be performed without the use of special processing technology. It is compatible with current 2D technology.
Since transistors can be precisely located on a crystal grain, transistors with single crystal performance can be formed on polysilicon films with precise control. Thus, the present invention makes it possible to solve the problem of poor performance of transistors formed on polysilicon film.
Furthermore, the present invention makes it possible for one or more layers of circuit elements to be formed on top of any existing structure, such as MEMS (micro-electrical mechanical systems). The underlying structures may, for example, me planar or non-planar.